The present invention generally relates to a programmable logic device and in particular to a programmable logic device which includes a verify circuit for a macro-cell and signal control in accordance with storage contents of programmable non-volatile memory elements.
A programmable logic array such as a programmable logic array device (hereafter simply referred to PLA device) or a programmable array logic (PAL device) has switches and programmable non-volatile memory elements such as erasable and programmable read only memory cells (hereafter simply referred to as EPROM cells). Switches are used for opening and closing corresponding signal lines or for selecting specific, individual signals therefrom. Each of the switches is controlled in accordance with information storage content of the corresponding programmable non-volatile memory element. The associated programmable non-volatile memory elements and the switches comprise a control circuit block which establishes and alters logic connections such as a signal input/output connection and an internal feedback connection. Such a control circuit block is hereafter referred to as a macro-cell. In general, the programmable logic array device includes a plurality of macro-cells.
Conventionally, for each of the non-volatile memory elements, there is provided a set of a write-in circuit, a read-out circuit and a power source switching circuit which is used for selectively supplying the write-in and read-out circuits with a power source voltage. In general, these circuits are made up of metal oxide semiconductor transistors (hereafter simply referred to as MOS transistors). In particular, the write-in circuit and the power source switching circuit must be constructed by MOS transistors having a high-voltage resistant ability. high-voltage standoff, or withstand, characteristic.
The conventional programmable logic device including the above macro-cell has the following disadvantages. First, in order for the programmable logic device to have an increased number of switches to thereby enhance functions thereof, a semiconductor chip having a greatly increased surface area must be used. This is because the write-in circuit, read-out circuit and power source switching circuit must be provided for each non-volatile memory element, and particularly the write-in circuit and the power source switching circuit are constructed by high-voltage resistant MOS transistors. Secondly, a test to check whether or not the write-in circuit and read-out circuit operate correctly, must be carried out for each of the non-volatile, memory elements. Therefore, a long time is required to test the device.